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Difference between revisions of "TM4C123 Using PLL"

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[[image:Tm4c_sysctl_rcc2_r.png|Run-Mode Clock Configuration RCC2]]
 
[[image:Tm4c_sysctl_rcc2_r.png|Run-Mode Clock Configuration RCC2]]
  
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{| class="wikitable" style="margin: auto; border-style: solid; border-width: 4px"
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|-
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! Bit<br /> Number !! Bit<br />Name !! Bit(s) Function
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|-
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| 6-4 || OSCSRC2 || Oscillator Source 2 (Selects the input source for the OSC)<br />'''Value'''  '''Description'''<br />0x0  MOSC (Main oscillator)<br />0x1  PIOSC (Precision internal oscillator)<br />0x2  PIOSC/4 (Precision internal oscillator / 4)<br />0x3  LFIOSC (Low-frequency internal oscillator)<br />0x4-0x6 Reserved<br />0x7  32.768 kHz (32.768-kHz external oscillator)
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|-
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| 11 || BYPASS2 || Example
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|-
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| 13 || PWRDN2 || Example
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|-
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| 22 || SYSDIV2LSB || Example
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|-
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| 28-23 || SYSDIV2 || Example
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|-
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| 30 || DIV400 || Example
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|-
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| 31 || USERCC2 || Example
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|-
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| Example || Example || Example
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|}
 
The RCC2 provides extend fields and functions compared with the RCC register. The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register so that additional larger divisors up to 64 are available to allow a lower system clock frequency to be used to improve the system Deep Sleep power consumption. The following Table shows how the SYSDIV2 encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1).
 
The RCC2 provides extend fields and functions compared with the RCC register. The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register so that additional larger divisors up to 64 are available to allow a lower system clock frequency to be used to improve the system Deep Sleep power consumption. The following Table shows how the SYSDIV2 encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1).
  

Revision as of 10:02, 30 January 2019

Using PLL

TM4C123GH6PM MCU has four different clock sources:

  1. Precision Internal Oscillator (PIOSC) : 16 MHz.
  2. Main Oscillator (MOSC) : It can use an external clock source or an external crystal.
  3. Low-Frequency Internal Oscillator (LFIOSC) : An on-chip internal 30 kHz Oscillator used for Deep-Sleep power-saving modes.
  4. Hibernate RTC Oscillator (RTCOSC) : It can be configured to be the 32.768 KHz external oscillator source from the Hibernation (HIB) module or the HIB Low-Frequency clock source (HIB LFIOSC), which is intended to provide the system with a real-time clock source.

Block Diagram

Block Diagram of the main clock tree on the TM4C including the PLL

The system clock is generated by a PLL that can be driven by any crystals or oscillators running between 5 and 25 MHz. The output frequency of the PLL is always 400 MHz, and it is independent on the input clock sources.

Two clock sources, Main OSC (MOSC) and Precision Internal osc (PIOSC) 16 MHz, can work as a clock source for the PLL, and this source can be selected via the MUX. Two multiplexers (MUXs) are used to select different clock sources, and two ways can be used to create a system clock to be used by the CPU:

  1. One way is to use the Phase-Locked Loop (PLL) clock generator that needs a clock source as the input source to create this system clock.
  2. Another way is to directly use any one of four clock sources, and this can be selected via a MUX. An easy way is to use Precision Internal OSC (16 MHz) divided by 4 to get a 4-MHz system clock.

When using the PLL, the output frequency of 400 MHz is pre-divided by 2 (becomes 200 MHz) before the user’s divisor is applied. Users can modify this 200-MHz system clock by adding different dividing factors in the SYSDIV in their program to use a lower-frequency system clock. The selected clock source can avoid the SYSDIV and USESYSDIV dividing operations via BYPASS for both MUXs and can be directly sent out as the system clock.

Two registers, Run-Mode Clock Configuration (RCC) register and Run-Mode Clock Configuration 2 (RCC2) register, provide controls for the system clock. The RCC2 register is used to provide additional control parameters that offer additional encodings over the RCC register. These registers control the following clock functionality:

  • Source of clocks in sleep and deep-sleep modes
  • System clock derived from PLL or other clock source
  • Enable or disable the oscillators and PLL
  • Clock divisors
  • Crystal input selection

Run-Mode Clock Configuration (SYSCTL_RCC_R)

Run-Mode Clock Configuration RCC

Bit
Number
Bit
Name
Bit Function
0 MOSCDIS 0: The main oscillator is enabled
1: The main oscillator is disabled—Default
5-4 OSCSRC Oscillator Source Selection:
0x0: Main Oscillator (MOSC)
0x1: Precision Internal Oscillator (PIOSC)—Default
0x2: Precision Internal Oscillator/4 (PIOSC/4)
0x3: Low-Frequency Internal Oscillator (LFIOSC)
11 BYPASS 0: The system clock uses the PLL output clock divided by the
divisor specified by SYSDIV (bits 26–23 in this register)
1: The system clock uses the OSC source and divided by the
divisor specified by SYSDIV (bits 26–23 in this register)
13 PWRDN 0: The PLL is operating normally
1: The PLL is powered down. Make sure that another clock
source is functioning and that the BYPASS bit is set before
setting this bit
22 USESYSDIV 0: The system clock is used undivided
1: The system clock divider is used for the system clock.
The system clock divider is forced to be used when the PLL is
selected as the source
26-23 SYSDIV System Clock Divisor
Specifies which divisor is used to generate the system clock from
either the PLL output or from the oscillator source, depending on
how the BYPASS bit in this register is configured.
27 ACG 0: The Run-Mode Clock Gating Control (RCGCn) registers are
used when the microcontroller enters a sleep mode
1: The SCGCn or DCGCn registers are used to control the clocks
distributed to the peripherals when the microcontroller is in a
sleep mode.

In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source. When using the PLL, the VCO frequency of 400 MHz is pre-divided by 2 before the divisor is applied.

SYSDIV DIVISOR Frequency
BYPASS=0
Frequency
BYPASS=1
Symbolic Definition
(Tivaware)
0x0 ÷1 Reserved Clock source frequency/1 SYSCTL_SYSDIV_1
0x1 ÷2 Reserved Clock source frequency/2 SYSCTL_SYSDIV_2
0x2 ÷3 66.67 MHz Clock source frequency/3 SYSCTL_SYSDIV_3
0x3 ÷4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4
0x4 ÷5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5
0x5 ÷6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6
0x6 ÷7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7
0x7 ÷8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8
0x8 ÷9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9
0x9 ÷10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10
0xA ÷11 18.18 Clock source frequency/11 SYSCTL_SYSDIV_11
0xB ÷12 16.67 MHz Clock source frequency/12 SYSCTL_SYSDIV_12
0xC ÷13 15.38 MHz Clock source frequency/13 SYSCTL_SYSDIV_13
0xD ÷14 14.29 MHz Clock source frequency/14 SYSCTL_SYSDIV_14
0xE ÷15 13.33 MHz Clock source frequency/15 SYSCTL_SYSDIV_15
0xF ÷16 12.5 MHz
Default
Clock source frequency/16 SYSCTL_SYSDIV_16

The XTAL (bits 6-10) field specifies Crystal Frequency and is given in the following table.

XTAL Crystal Freq (MHz) XTAL Crystal Freq (MHz) XTAL Crystal Freq (MHz)
0x4 3.579545 MHz 0xC 6.144 MHz 0x14 14.31818 MHz
0x5 3.6864 MHz 0xD 7.3278 MHz 0x15 16.0 MHz
0x06 4 MHz 0xE 8 MHz 0x16 16.384 MHz
0x7 4.096 MHz 0xF 8.192 MHz 0x17 18.0 MHz
0x8 4.9152 MHz 0x10 10.0 MHz 0x18 20.0 MHz
0x9 5 MHz 0x11 12.0 MHz 0x19 24.0 MHz
0xA 5.12 MHz 0x12 12.288 MHz 0x1A 25.0 MHz
0xB 6 MHz (reset value) 0x13 13.56 MHz others reserved

Run-Mode Clock Configuration 2 (SYSCTL_RCC2_R)

Run-Mode Clock Configuration RCC2

Bit
Number
Bit
Name
Bit(s) Function
6-4 OSCSRC2 Oscillator Source 2 (Selects the input source for the OSC)
Value Description
0x0 MOSC (Main oscillator)
0x1 PIOSC (Precision internal oscillator)
0x2 PIOSC/4 (Precision internal oscillator / 4)
0x3 LFIOSC (Low-frequency internal oscillator)
0x4-0x6 Reserved
0x7 32.768 kHz (32.768-kHz external oscillator)
11 BYPASS2 Example
13 PWRDN2 Example
22 SYSDIV2LSB Example
28-23 SYSDIV2 Example
30 DIV400 Example
31 USERCC2 Example
Example Example Example

The RCC2 provides extend fields and functions compared with the RCC register. The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register so that additional larger divisors up to 64 are available to allow a lower system clock frequency to be used to improve the system Deep Sleep power consumption. The following Table shows how the SYSDIV2 encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1).

When the RCC2 is used, it will override the functions provided by the RCC register.

SYSDIV2 DIVISOR Frequency
BYPASS2=0
Frequency
BYPASS2=1
Symbolic Definition
(Tivaware)
0x0 ÷1 Reserved Clock source frequency/1 SYSCTL_SYSDIV_1
0x1 ÷2 Reserved Clock source frequency/2 SYSCTL_SYSDIV_2
0x2 ÷3 66.67 MHz Clock source frequency/3 SYSCTL_SYSDIV_3
0x3 ÷4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4
0x4 ÷5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5
... ... ... .... ...
0x9 ÷10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10
... ... ... ... ...
0x3F ÷64 3.125 MHz Clock source frequency/64 SYSCTL_SYSDIV_64

Raw Interrupt Status (RIS)

Raw Interrupt Status (RIS)

Programming the PLL

The Main Oscillator (MOSC) for the TM4C on the evaluation board is 16 MHz. This means the reference clock (Ref Clk) input to the phase/frequency detector will be 16 MHz. For a 16 MHz crystal, we set the XTAL bits to 10101 (0x15). We use RCC2 because it provides more options

  1. Configure the system to use RCC2 (SYSCTL_RCC2_R)for advanced features. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used.
  2. Set BYPASS2 (bit 11), thereby configuring the microcontroller to run off a "raw" clock source and following for the new PLL configuration to be validated before switching the system clock to the PLL.
  3. Specify the crystal frequency in the four XTAL bits. The OSCSRC2 bits are cleared to select the main oscillator as the oscillator clock source.
  4. Clear PWRDN2 (bit 13) to activate the PLL.
  5. Configure and enable the clock divider using the 7-bit SYSDIV2 field. If the 7-bit SYSDIV2 is n, then the clock will be divided by n+1. To get the desired 80 MHz from the 400 MHz PLL, we need to divide by 5. So, we place a 4 into the SYSDIV2 field.
  6. Wait for the PLL to stabilize by waiting for PLLRIS (bit 6) in the SYSCTL_RIS_R to become high.
  7. Connect the PLL by clearing the BYPASS2 bit.


PLL Source Code

  1. #include <stdint.h>
  2. #include "inc/tm4c123gh6pm.h"
  3.  
  4. #define SYSCTL_RIS_PLLLRIS      0x00000040  /* PLL Lock Raw Interrupt Status */
  5. #define SYSCTL_RCC_XTAL_M       0x000007C0  /* Crystal Value */
  6. #define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  /* 6 MHz Crystal */
  7. #define SYSCTL_RCC_XTAL_8MHZ    0x00000380  /* 8 MHz Crystal */
  8. #define SYSCTL_RCC_XTAL_16MHZ   0x00000540  /* 16 MHz Crystal */
  9. #define SYSCTL_RCC2_USERCC2     0x80000000  /* Use RCC2 */
  10. #define SYSCTL_RCC2_DIV400      0x40000000  /* Divide PLL as 400 MHz vs. 200 MHz */
  11. #define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  /* System Clock Divisor 2 */
  12. #define SYSCTL_RCC2_SYSDIV2LSB  0x00400000  /* Additional LSB for  SYSDIV2 */
  13. #define SYSCTL_RCC2_PWRDN2      0x00002000  /* Power-Down PLL 2 */
  14. #define SYSCTL_RCC2_BYPASS2     0x00000800  /* PLL Bypass 2 */
  15. #define SYSCTL_RCC2_OSCSRC2_M   0x00000070  /* Oscillator Source 2 */
  16. #define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  /* MOSC */
  17.  
  18. /* configure the system to get its clock from the PLL
  19. * SYSDIV = 400/freq -1
  20. * bus frequency is 400MHz/(SYSDIV+1)
  21. */
  22.  
  23. void PLL_Init(void)
  24. {
  25.   /* 1) configure the system to use RCC2 for advanced features
  26.       such as 400 MHz PLL and non-integer System Clock Divisor */
  27.   SYSCTL_RCC2_R |= SYSCTL_RCC2_USERCC2;
  28.   /* 2) bypass PLL while initializing */
  29.   SYSCTL_RCC2_R |= SYSCTL_RCC2_BYPASS2;
  30.   /* 3) select the crystal value and oscillator source */
  31.   SYSCTL_RCC_R &= ~SYSCTL_RCC_XTAL_M;   	/* clear XTAL field */
  32.   SYSCTL_RCC_R += SYSCTL_RCC_XTAL_16MHZ;	/* configure for 16 MHz crystal */
  33.   SYSCTL_RCC2_R &= ~SYSCTL_RCC2_OSCSRC2_M;	/* clear oscillator source field */
  34.   SYSCTL_RCC2_R += SYSCTL_RCC2_OSCSRC2_MO;	/* configure for main oscillator source */
  35.   /* 4) activate PLL by clearing PWRDN */
  36.   SYSCTL_RCC2_R &= ~SYSCTL_RCC2_PWRDN2;
  37.   /* 5) set the desired system divider and the system divider least significant bit */
  38.   SYSCTL_RCC2_R |= SYSCTL_RCC2_DIV400;  	/* use 400 MHz PLL */
  39.   SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~0x1FC00000)   /* clear system clock divider field */
  40.                   + (4<<22);      	        /* configure for 80 MHz clock */
  41.   /* 6) wait for the PLL to lock by polling PLLLRIS */
  42.   while((SYSCTL_RIS_R&SYSCTL_RIS_PLLLRIS)==0){
  43.       ;
  44.   }
  45.   /* 7) enable use of PLL by clearing BYPASS */
  46.   SYSCTL_RCC2_R &= ~SYSCTL_RCC2_BYPASS2;
  47. }