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Difference between revisions of "TM4C123 Using PLL"

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| 0x400FE060 || SYSDIV || USESYSDIV || PWRDN || BYPASS || XTAL || OSCSRC || SYSCTL_RCC_R
 
| 0x400FE060 || SYSDIV || USESYSDIV || PWRDN || BYPASS || XTAL || OSCSRC || SYSCTL_RCC_R
 
|}
 
|}
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source. When using the PLL, the VCO frequency of 400 MHz is pre-divided by 2 before the divisor is applied.
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In the '''RCC''' register, the '''SYSDIV''' field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source. When using the PLL, the VCO frequency of 400 MHz is pre-divided by 2 before the divisor is applied. The '''XTAL''' (bits 6-10) field specifies Crystal Frequency and is given in the following table.
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{| class="wikitable"
 +
|-
 +
! XTAL !! Crystal Freq (MHz) !! XTAL !! Crystal Freq (MHz) !! XTAL !! Crystal Freq (MHz)
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|-
 +
| 0x4 || 3.579545 MHz || 0xC || 6.144 MHz || 0x14 || 14.31818 MHz
 +
|-
 +
| 0x5 || 3.6864 MHz || 0xD || 7.3278 MHz || '''0x15''' || '''16.0 MHz'''
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|-
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| 0x06 || 4 MHz || 0xE || 8 MHz || 0x16 || 16.384 MHz
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|-
 +
| 0x7 || 4.096 MHz || 0xF || 8.192 MHz || 0x17 || 18.0 MHz
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|-
 +
| 0x8 || 4.9152 MHz || 0x10 || 10.0 MHz || 0x18 || 20.0 MHz
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|-
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| 0x9 || 5 MHz || 0x11 || 12.0 MHz || 0x19 || 24.0 MHz
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|-
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| 0xA || 5.12 MHz || 0x12 || 12.288 MHz || 0x1A || 25.0 MHz
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|-
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| 0xB || 6 MHz (reset value) || 0x13 || 13.56 MHz || others || reserved
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|}
  
 
'''Run-Mode Clock Configuration 2 (SYSCTL_RCC2_R)'''
 
'''Run-Mode Clock Configuration 2 (SYSCTL_RCC2_R)'''
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[[image:tm4c_ris.jpg|690px|Raw Interrupt Status (RIS)]]
 
[[image:tm4c_ris.jpg|690px|Raw Interrupt Status (RIS)]]
  
{| class="wikitable"
 
|-
 
! XTAL !! Crystal Freq (MHz) !! XTAL !! Crystal Freq
 
|-
 
| 0x4 || 3.579545 MHz|| 0x10 || 10.0 MHz
 
|-
 
| 0x5 || 3.6864 MHz || 0x11 || 12.0 MHz
 
|-
 
| 0x06 || 4 MHz || 0x12 || 12.288 MHz
 
|-
 
| 0x7 || 4.096 MHz || 0x13 || 13.56 MHz
 
|-
 
| 0x8 || 4.9152 MHz || 0x14 || 14.31818 MHz
 
|-
 
| 0x9 || 5 MHz || 0x15 | MHz || 16.0 MHz
 
|-
 
| 0xA || 5.12 MHz|| 0x16 || 16.384 MHz
 
|-
 
| 0xB || 6 MHz (reset value) || 0x17 || 18.0 MHz
 
|-
 
| 0xC || 6.144 MHz || 0x18 || 20.0 MHz
 
|-
 
| 0xD || 7.3278 MHz || 0x19 || 24.0 MHz
 
|-
 
| 0xE || 8 MHz || 0x1A || 25.0 MHz
 
|-
 
| 0xF || 8.192 MHz || others || reserved
 
|}
 
 
==== Source Code ====
 
==== Source Code ====
 
<syntaxhighlight lang="c" line start="1">
 
<syntaxhighlight lang="c" line start="1">

Revision as of 05:42, 6 December 2017

Using PLL

TM4C123GH6PM MCU has four different clock sources:

  1. Precision Internal Oscillator (PIOSC)
    16 MHz.
  2. Main Oscillator (MOSC)
    It can use an external clock source or an external crystal.
  3. Low-Frequency Internal Oscillator (LFIOSC)
    An on-chip internal 30-kHz Oscillator used for Deep-Sleep power-saving modes.
  4. Hibernate RTC Oscillator (RTCOSC)
    It can be configured to be the 32.768 KHz external oscillator source from the Hibernation (HIB) module or the HIB Low-Frequency clock source (HIB LFIOSC), which is intended to provide the system with a real-time clock source.

Block Diagram

Block Diagram of the main clock tree on the TM4C including the PLL

The system clock is generated by a PLL that can be driven by any crystals or oscillators running between 5 and 25 MHz. The output frequency of the PLL is always 400 MHz, and it is independent on the input clock sources.

Two clock sources, Main OSC (MOSC) and Precision Internal osc (PIOSC) 16 MHz, can work as a clock source for the PLL, and this source can be selected via the MUX. Two multiplexers (MUXs) are used to select different clock sources, and two ways can be used to create a system clock to be used by the CPU:

  1. One way is to use the Phase-Locked Loop (PLL) clock generator that needs a clock source as the input source to create this system clock.
  2. Another way is to directly use any one of four clock sources, and this can be selected via a MUX. An easy way is to use Precision Internal OSC (16 MHz) divided by 4 to get a 4-MHz system clock.
  • The Main Oscillator (MOSC) for the TM4C on the evaluation board is 16 MHz. This means the reference clock input to the phase/frequency detector will be 16 MHz.
  • When using the PLL, the output frequency of 400 MHz is pre-divided by 2 (becomes 200 MHz) before the user’s divisor is applied. Users can modify this 200-MHz system clock by adding different dividing factors in the SYSDIV in their program to use a lower-frequency system clock.
  • The selected clock source can avoid the SYSDIV and USESYSDIV dividing operations via BYPASS for both MUXs and can be directly sent out as the system clock.

Two registers, Run-Mode Clock Configuration (RCC) register and Run-Mode Clock Configuration 2 (RCC2) register, provide controls for the system clock. The RCC2 register is used to provide additional control parameters that offer additional encodings over the RCC register. These registers control the following clock functionality:

  • Source of clocks in sleep and deep-sleep modes
  • System clock derived from PLL or other clock source
  • Enable or disable the oscillators and PLL
  • Clock divisors
  • Crystal input selection

Run-Mode Clock Configuration (SYSCTL_RCC_R)

Run-Mode Clock Configuration RCC

Address 26-23 22 13 11 10-6 5-4 NAME
0x400FE060 SYSDIV USESYSDIV PWRDN BYPASS XTAL OSCSRC SYSCTL_RCC_R

In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source. When using the PLL, the VCO frequency of 400 MHz is pre-divided by 2 before the divisor is applied. The XTAL (bits 6-10) field specifies Crystal Frequency and is given in the following table.

XTAL Crystal Freq (MHz) XTAL Crystal Freq (MHz) XTAL Crystal Freq (MHz)
0x4 3.579545 MHz 0xC 6.144 MHz 0x14 14.31818 MHz
0x5 3.6864 MHz 0xD 7.3278 MHz 0x15 16.0 MHz
0x06 4 MHz 0xE 8 MHz 0x16 16.384 MHz
0x7 4.096 MHz 0xF 8.192 MHz 0x17 18.0 MHz
0x8 4.9152 MHz 0x10 10.0 MHz 0x18 20.0 MHz
0x9 5 MHz 0x11 12.0 MHz 0x19 24.0 MHz
0xA 5.12 MHz 0x12 12.288 MHz 0x1A 25.0 MHz
0xB 6 MHz (reset value) 0x13 13.56 MHz others reserved

Run-Mode Clock Configuration 2 (SYSCTL_RCC2_R)

Run-Mode Clock Configuration RCC2

Address 31 30 28-23 13 11 6-4 NAME
0x400FE070 USERCC2 DIV400 SYSDIV2 PWRDN2 BYPASS2 OSCSRC2 SYSCTL_RCC2_R

Raw Interrupt Status (RIS)

Raw Interrupt Status (RIS)

Source Code

  1. #include <stdint.h>
  2. #include "inc/tm4c123gh6pm.h"
  3.  
  4. // initializes the PLL to the desired frequency.
  5.  
  6. // bus frequency is 400MHz/(SYSDIV2+1) = 400MHz/(7+1) = 50 MHz
  7. // 
  8.  
  9. #define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
  10. #define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal Value
  11. #define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz Crystal
  12. #define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz Crystal
  13. #define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16 MHz Crystal
  14. #define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
  15. #define SYSCTL_RCC2_DIV400      0x40000000  // Divide PLL as 400 MHz vs. 200 MHz
  16. #define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
  17. #define SYSCTL_RCC2_SYSDIV2LSB  0x00400000  // Additional LSB for SYSDIV2
  18. #define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
  19. #define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
  20. #define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
  21. #define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
  22.  
  23. // configure the system to get its clock from the PLL
  24. // SYSDIV = 400/freq -1
  25. // bus frequency is 400MHz/(SYSDIV+1)
  26. void PLL_Init(void)
  27. {
  28.     // 0) configure the system to use RCC2 for advanced features
  29.     //    such as 400 MHz PLL and non-integer System Clock Divisor
  30.     SYSCTL_RCC2_R |= SYSCTL_RCC2_USERCC2;
  31.     // 1) bypass PLL while initializing
  32.     SYSCTL_RCC2_R |= SYSCTL_RCC2_BYPASS2;
  33.     // 2) select the crystal value and oscillator source
  34.     SYSCTL_RCC_R &= ~SYSCTL_RCC_XTAL_M;   // clear XTAL field
  35.     SYSCTL_RCC_R += SYSCTL_RCC_XTAL_16MHZ;// configure for 16 MHz crystal
  36.     SYSCTL_RCC2_R &= ~SYSCTL_RCC2_OSCSRC2_M;// clear oscillator source field
  37.     SYSCTL_RCC2_R += SYSCTL_RCC2_OSCSRC2_MO;// configure for main oscillator source
  38.     // 3) activate PLL by clearing PWRDN
  39.     SYSCTL_RCC2_R &= ~SYSCTL_RCC2_PWRDN2;
  40.     // 4) set the desired system divider and the system divider least significant bit
  41.     SYSCTL_RCC2_R |= SYSCTL_RCC2_DIV400;  // use 400 MHz PLL
  42.     SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~0x1FC00000) // clear system clock divider field
  43.                   + (4<<22);      // configure for 80 MHz clock
  44.     // 5) wait for the PLL to lock by polling PLLLRIS
  45.     while((SYSCTL_RIS_R&SYSCTL_RIS_PLLLRIS)==0){};
  46.     // 6) enable use of PLL by clearing BYPASS
  47.     SYSCTL_RCC2_R &= ~SYSCTL_RCC2_BYPASS2;
  48. }