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TM4C123G LaunchPad UART Interrupt Programming

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UART0 Interrupt Programming

Examining the UARTIM (UART Interrupt Mask) register, we see bit 4 allows us to enable the receive interrupt. If the receive interrupt for UART is enabled, when a byte is received, the receive flag is directed to NVIC and that causes the interrupt handler associated with the UART0 to be executed. In the UART0 handler we must read the received byte and clear the interrupt flag.

Tm4c uartim r.png

bit Name Description
1 CTSIM UART Clear to Send Modem Interrupt Mask
1: An interrupt is sent to the interrupt controller when the CTSRIS bit in the UARTRIS register is set.
0: The CTSRIS interrupt is suppressed and not sent to the interrupt controller.
4 RXIM UART Receive Interrupt Mask
1: An interrupt is sent to the interrupt controller when the RXRIS bit in the UARTRIS register is set.
0: The RXRIS interrupt is suppressed and not sent to the interrupt controller.
5 TXIM UART Transmit Interrupt Mask
1: An interrupt is sent to the interrupt controller when the TXRIS bit in the UARTRIS register is set.
0: The TXRIS interrupt is suppressed and not sent to the interrupt controller.
6 RTIM UART Receive Time-Out Interrupt Mask
1: An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set
0: The RTRIS interrupt is suppressed and not sent to the interrupt controller.
7 FEIM UART Framing Error Interrupt Mask
1: An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set.
0: The FERIS interrupt is suppressed and not sent to the interrupt controller.
8 PEIM UART Parity Error Interrupt Mask
1: An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set.
0: The PERIS interrupt is suppressed and not sent to the interrupt controller.
9 BEIM UART Break Error Interrupt Mask
1: An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set.
0: The BERIS interrupt is suppressed and not sent to the interrupt controller.
10 OEIM UART Overrun Error Interrupt Mask
1: An interrupt is sent to the interrupt controller when the OERIS bit in the UARTRIS register is set.
0: The OERIS interrupt is suppressed and not sent to the interrupt controller.
12 9BITIM 9-Bit Mode Interrupt Mask
1: An interrupt is sent to the interrupt controller when the 9BITRIS bit in the UARTRIS register is set.
0: The 9BITRIS interrupt is suppressed and not sent to the interrupt controller.
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