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TM4C123GXL PLL Sample Program

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PLL Sample Program

  1. /* Configure the system to get its clock from the PLL */
  2.  
  3. #include <stdint.h>
  4. #include "inc/tm4c123gh6pm.h"
  5.  
  6. #define SYSCTL_RIS_PLLLRIS      0x00000040  /* PLL Lock Raw Interrupt Status */
  7. #define SYSCTL_RCC_XTAL_M       0x000007C0  /* Crystal Value */
  8. #define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  /* 6 MHz Crystal */
  9. #define SYSCTL_RCC_XTAL_8MHZ    0x00000380  /* 8 MHz Crystal */
  10. #define SYSCTL_RCC_XTAL_16MHZ   0x00000540  /* 16 MHz Crystal */
  11. #define SYSCTL_RCC2_USERCC2     0x80000000  /* Use RCC2 */
  12. #define SYSCTL_RCC2_DIV400      0x40000000  /* Divide PLL as 400 MHz vs. 200 MHz */
  13. #define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  /* System Clock Divisor 2 */
  14. #define SYSCTL_RCC2_SYSDIV2LSB  0x00400000  /* Additional LSB for  SYSDIV2 */
  15. #define SYSCTL_RCC2_PWRDN2      0x00002000  /* Power-Down PLL 2 */
  16. #define SYSCTL_RCC2_BYPASS2     0x00000800  /* PLL Bypass 2 */
  17. #define SYSCTL_RCC2_OSCSRC2_M   0x00000070  /* Oscillator Source 2 */
  18. #define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  /* MOSC */
  19.  
  20. #define Bus80MHz     4
  21.  
  22. void PLL_Init(void)
  23. {
  24.   /* 1) configure the system to use RCC2 for advanced features
  25.       such as 400 MHz PLL and non-integer System Clock Divisor */
  26.   SYSCTL_RCC2_R |= SYSCTL_RCC2_USERCC2;
  27.   /* 2) bypass PLL while initializing */
  28.   SYSCTL_RCC2_R |= SYSCTL_RCC2_BYPASS2;
  29.   /* 3) select the crystal value and oscillator source */
  30.   SYSCTL_RCC_R &= ~SYSCTL_RCC_XTAL_M;   	/* clear XTAL field */
  31.   SYSCTL_RCC_R += SYSCTL_RCC_XTAL_16MHZ;	/* configure for 16 MHz crystal */
  32.   SYSCTL_RCC2_R &= ~SYSCTL_RCC2_OSCSRC2_M;	/* clear oscillator source field */
  33.   SYSCTL_RCC2_R += SYSCTL_RCC2_OSCSRC2_MO;	/* configure for main oscillator source */
  34.   /* 4) activate PLL by clearing PWRDN */
  35.   SYSCTL_RCC2_R &= ~SYSCTL_RCC2_PWRDN2;
  36.   /* 5) set the desired system divider and the system divider least significant bit */
  37.   SYSCTL_RCC2_R |= SYSCTL_RCC2_DIV400;  	/* use 400 MHz PLL */
  38.   SYSCTL_RCC2_R = (SYSCTL_RCC2_R&~0x1FC00000)   /* clear system clock divider field */
  39.                   + (Bus80MHz<<22);      	/* configure for 80 MHz clock */
  40.   /* 6) wait for the PLL to lock by polling PLLLRIS */
  41.   while((SYSCTL_RIS_R&SYSCTL_RIS_PLLLRIS)==0){
  42.       ;
  43.   }
  44.   /* 7) enable use of PLL by clearing BYPASS */
  45.   SYSCTL_RCC2_R &= ~SYSCTL_RCC2_BYPASS2;
  46. }